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Parallel ATA (PATA)

Part 2 - Signals

Table of contents for the Parallel ATA (PATA and PATAPI) pages:

• Part 1 - Introduction
• Part 2 - Signals
• Part 3 - Registers
• Part 4 - Protocols
• Part 5 - Commands
• Part 6 - DMA
• Part 7 - Host Programming
• Part 8 - Embedded Systems

Signals

The following table shows the PATA interface signals.

Signal	Use
CS0-, CS1-, DA2, DA1, DA0	Address signals. CS0- is used to address the ATA Command Block registers. CS1- is used to address the ATA Control Block registers. The DAx signals select the register within the Command or Control block set of registers.
IOR- and IOW-	I/O Read and Write. Tells the device if the selected register is being read by the host or written by the host.
DD15 - DD0	Bidirectional 16-bit data bus. Only DD7 - DD0 are used when reading or writing one of the 8-bit Command or Control block registers. DD15 - DD0 are used only when reading or writing the ATA Data register during PIO data transfers.

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Page updated 28 Dec 2005.