[Home] | [Products] |
ATA-ATAPI.COM DOES NOT manufacture, sell or support any hardware products.
|
Technical Support email address: After checking this page if you still have a question or problem send an email to
|
This page contains bug lists and usage suggestions for NVMEQRWT, NVMETEST, AHCCMDT, AHCDEMO, AHCNCQT, ATACT and ATADEMO.
System physical memory corruption and system crash. NVME has a very basic and very bad design problem. If the host OS and NVME drive do not interpret the usage of the PRP1 and PRP2 memory addresses the same then there wlll be corruption of system memory and the resulting crash of the system's OS. I see this all the time while testing. I don't think I've ever seen an I/O interface that has such a serious system and data integrity issue. |
Firmware Download problem. If you start a Firmware Download and there is some problem or the download and commit are not completed it may not be possible to start another download because the second may get an invalid offset error. The question is this: Should a Firmware Download with offset of zero start a new download even if a previous download was started but not completed? Or is a reset required before attempting the second download? |
Setting values in a controller register such as the CC register. There are several configuration bits in the CC register that can be set only while CC.EN is 0. The assumption is that you must write these values plus CC.EN set to 0. But then when you set CC.EN to 1 you must repeat all the other values in that write? Assuming this is true then the NVME specification should be more clear about this and simplely say all the CC configuration values must be set when any write to the CC register sets CC.EN to 1. |
CMBLOC and CMBSZ registers. In the CMBLOC register the OFST field is an offset from an undefined location. Is it an offset from the NVME registers (offset from CAP register) or an offset from some other location in physical memory. The NVME specification does not say which. |
HMPRE and HMMIN fields of Identify CNS=1 data. There are NO references to the HMPRE or HMMIN fields any where in the NVME specification. How are these fields related to the Set Feature 0Dh command? |
This is the example Script List (SLIST). See the SLIST command description in the AHCDEMO or NVMETEST User Guide. This SLIST example simply uses SAY commands to trace the execution sequence of the SLIST. To install and execute this example follow these steps:
|
None known at this time in current version. Please the NVME issues above. |
None at this time. Please the NVME issues above. |
None known at this time in current version. Please the NVME issues above. |
See the script files BASIC0.DSF, WRC0.DSF and FWDL.DSF these are good examples of script files. Please the NVME issues above. |
None known at this time in current version. |
NOTICE: Marvell 88SE6145 AHCI Controller: This model controller (Vendor ID 11AB) identifies itself as AHCI but it really is not AHCI compatible. While it may appear to operate for a few commands, it will normally not work with AHCCMDT. This controller is found on some Intel motherboards as a second AHCI (RAID?) controller. |
SEQ=N vs. SEQ=WRN option and data compare errors: Running AHCCMDT with SEQ=N (the program's default) can make locating the source of data compare problems more difficult to find in the drive's hardware and/or firmware. Use SEQ=WRN to see if the problem that can be found using only a write pass followed by a read pass. If there are no data compare errors, then use SEQ=N. |
MINLBA and MAXLBA options: Use these options to test less than the full drive. For example, if you have a drive with 400M sectors (about 200GB) you could use these options to test the first 10GB (about 20M sectors), the middle 10GB or the last 10GB:
|
None known at this time in current version. |
NOTICE: Marvell 88SE6145 AHCI Controller: This model controller (Vendor ID 11AB) identifies itself as AHCI but it really is not AHCI compatible. While it may appear to operate for a few commands, it will normally not work with AHCCMDT. This controller is found on some Intel motherboards as a second AHCI (RAID?) controller. |
See the script file WRC4.DSF - this is a very useful Write/Read/Compare script! |
None known at this time in current version. |
NOTICE: Marvell 88SE6145 AHCI Controller: This model controller (Vendor ID 11AB) identifies itself as AHCI but it really is not AHCI compatible. While it may appear to operate for a few commands, it will normally not work with AHCCMDT. This controller is found on some Intel motherboards as a second AHCI (RAID?) controller. |
SEQ=N vs. SEQ=WRN option and data compare errors: Running AHCNCQT with SEQ=N (the program's default) can make locating the source of data compare problems more difficult to find in the drive's hardware and/or firmware. Use SEQ=WRN to see if the problem that can be found using only a write pass followed by a read pass. If there are no data compare errors, then use SEQ=N. |
MINLBA and MAXLBA options: Use these options to test less than the full drive. For example, if you have a drive with 400M sectors (about 200GB) you could use these options to test the first 10GB (about 20M sectors), the middle 10GB or the last 10GB:
|
Usage of command line options P0, P1, S0 and S1 - (without the PCI bus numbers b:d:f) will disable the use of read/write DMA commands. This was initially entered as a bug in version 4N but it is not a bug. When the PROMPT option was added, the functionality of these options was changed but the User Guide and history files did not indicate this change. When using version 4N (and future versions) use either the b:d:f:x option, or the PROMPT option, then use of the read/write DMA commands will be possible. |
SEQ=N vs. SEQ=WRN option and data compare errors: Running ATACT with SEQ=N (the program's default) can make locating the source of data compare problems more difficult to find in the drive's hardware and/or firmware. Use SEQ=WRN to see if the problem that can be found using only a write pass followed by a read pass. If there are no data compare errors, then use SEQ=N -- It is possible that more random write/read and other randomly executed commands, such as the power management commands, are required to create the data compare error. |
MAXSIZE and MINLBA options: Use these options to test less than the full drive. For example, if you have a drive with 400M sectors (about 200GB) you could use these options to test the first 10GB (about 20M sectors), the middle 10GB or the last 10GB:
|
The DUMPCHT option - finding data compare errors that happen during the SEQ=R pass: When using SEQ=WRN you are getting a data compare error during the SEQ=R pass that seems to have happened during the SEQ=W pass. Of course the write commands that caused the problem are no longer in the Commmand History Trace (CHT). But every sector that is written contains the command number that wrote the sector. For example, when some sector is read it contains the wrong data (the data for some other LBA) - using the command number in this incorrect sector, rerun the program with the same command line options and add the DUMPCHT=n option, where n is about 30 more than the command number in the sector with the incorrect data. This will cause the Command History Trace (CHT) to be displayed during the SEQ=W pass at the write command about 30 commands following the command that wrote the bad data. Of course DUMPCHT=n can be using at other times, not just to find problems in a SEQ=W pass. |
Usage of command line options P0, P1, S0 and S1 in version 11N - (without the PCI bus numbers b:d:f) will disable the use of read/write DMA commands. This was initially entered as a bug in version 11N but it is not a bug. When the PROMPT option was added, the functionality of these options was changed but the User Guide and history files did not indicate this change. When using version 11N (and future versions) use either the b:d:f:x option, or the PROMPT option, then use of the read/write DMA commands will be possible. |
None at this time. |
Technical Support email address: After checking this page if you still have a question or problem send an email to
|
Page updated 22 Dec 2018.